There has been widely used a conductivity modulated MOS FET of a lateral type inner semiconductor integrated circuit in which circuit elements are separated from the other by an isolation region. Although the conductivity modulated MOS FET will be explained in detail later, it comprises an island region of an N.sup.- epitaxial layer encircled on a P-substrate having an N.sup.+ -buried layer by a P.sup.+ -isolation region, a P.sup.+ -drain region and a P.sup.- base region respectively formed on the island region, an N.sup.+ -source region and a P.sup.+ -backgate region respectively formed on the P.sup.- -base region, a polysilicon gate electrode provided on a gate insulation film formed on a peripheral edge of the P.sup.- -base region, a drain electrode provided on the P.sup.+ -drain region, and a source electrode provided on the N.sup.+ -source region and the P.sup.+ -backgate region to be in contact therewith.
In the conductivity modulated MOS FET, when a positive voltage is applied to the gate electrode, a channel is formed on a surface of the P.sup.- -base region so that a MOS FET including a source of the N.sup.+ -source region and a drain of the N.sup.- -epitaxial layer operates. When the MOS FET is under a state of a conduction, the drain electrode is under the application of a positive voltage so that holes are injected from the P.sup.+ -drain region to the N.sup.- -epitaxial layer, and a lateral bipolar transistor in which the P.sup.+ -drain region is an emitter, the N.sup.- -epitaxial layer is a base, and the P.sup.- -base region is a collector is turned on. The low-density drain region of the N.sup.- -epitaxial layer is formed with a predetermined length to increase the withstand voltage between the drain electrode and the P.sup.- -base region. For this structure, the P.sup.+ -drain region 3 is provided to decrease the drain resistance which is further decreased in accordance with the turning-on of the lateral bipolar transistor.
According to the conductivity modulated MOS FET, however, there is a disadvantage that the efficiency of area is not so high as expected for the reason why the drain electrode and the source electrode are provided on the same plane of the substrate, although the structure is suitable for the increase of integrated density in an integration circuit as compared to a conductivity modulated MOS FET in which a drain electrode and a source electrode are provided on the opposite planes of a semiconductor substrate.